|Next Page of this Chapter|
In previous chapters we have looked at the basics behind sequential circuits. In this chapter we will look at the operating characteristics of four Flip-flops. Flip-flops are the first stage in sequential logic design which incorperates memory (storage of previous states).
Flip-flops that we will look at include the following:
After you have looked at the information about flip-flops, you can use some LabView simulations to get more familiar with how the flip-flops function. To start the simulations now, you should move onto the next webpage, Flip-Flop Simulations.
This type of flip-flop has two inputs: Set and Reset. Two outputs: Q and Q' (Q' being the inverse of Q). The SR flip-flop can also have a clock input for a level driven circuit as opposed to a pulse driven circuit.
The operation of an SR flip-flop is as follows: The Set input will
make Q goto 1 i.e. will 'set' the output. The Reset input will make
the output Q goto 0 i.e. reset the output.
Knowing the above, we can layout the operating characteristics and the state change table:
There are a few different ways SR flip-flops can be made. They can
be pulse driven or clock (and therefore level are used) driven. For
the state change diagram above either a pulse or level input can be
implied. When using the state change table to describe pulses, a '1'
implies a pulse should be applied, where '0' implies that no pulse should
exist at this state.
The T type flip-flop is a single input device: T (trigger). Two outputs: Q and Q' (where Q' is the inverse of Q).
The operation of the T type flip-flop is as follows: A '0' input to 'T' will make the next state the same as the present state (i.e. T = 0 present state = 0 therefore next state = 0). However a '1' input to 'T' will change the next state to the inverse of the present state (i.e. T = 1 present state = 0 therefore next state = 1).
Knowing the above, we can now formalise the operating characteristics and the state change table:
The T type flip-flop is an edge driven device. Therefore you should not associate 1 and 0 with levels, but instead 1 should be considered as a pulse, and 0 as no pulse.
Notice that if a clock signal was tied to T, the output Q would be a clock signal at approximatly half the frequency of T. This property makes the T flip-flop a good candidate for applications such as frequency division.
The D type flip-flop has one data input 'D' and a clock input. The circuit edge triggers on.the clock input. The flip-flop also has two outputs Q and Q' (where Q' is the reverse of Q).
The operation of the D type flip-flop is as follows: Any input appearing (present state) at the input D, will be produced at the output Q in time T+1 (next state). e.g. if in the present state we have D = 0 and Q = 1, the next state will be D = anything and Q = 0.
Knowing the above, we can now generate the state change table and the operating characteristics.
The operation of the D type delays any input by exactly one clock cycle (given an instantanious response time i.e. a perfect flip-flop). Cascading several D type flip-flops together can produce delaying circuits, possible applications could be for matching time delays in digital television systems.
The JK type flip-flop consists of two data inputs: J and K, and one clock input. There are again two outputs Q and Q' (where Q' is the reverse of Q).
The JK flip-flop operations are quite complicated to understand by text alone. So here we will simply see the operating characteristics diagram and then discuss it.
Knowing the above we can now construct the state change table:
Lets discuss this state change table with respect to the operating characteristics diagram. There actually exists two operating characteristics that satisfy every possible output combination. This means there should be some 'don't care' terms with each output combination (as our diagram shows). In the list below we shall see how each of the terms
The JK flip-flop can actually be reconfigured so that it can perform the operation of some of the other flip-flops that are discussed above. For example, if the two inputs J and K are tied together, then the output characteristics are fixed to A and D. This precisely matches the characteristics of a T type flip flop. Also to note, because the way a JK is made, you may replace an SR flip-flop with a JK flip-flop without a change in operation. However you cannot replace a JK flip-flop with an SR flip-flop as a S=1 R=1 condition is not allowed, but a J=1 K=1 condition is permitted.