Chapter 6. - Flip Flops

In previous chapters we have looked at the basics behind sequential circuits. In this chapter we will look at the operating characteristics of four Flip-flops. Flip-flops are the first stage in sequential logic design which incorperates memory (storage of previous states).

Flip-flops that we will look at include the following:

• SR type Flip-flop or Set / Reset
• T type Flip-flop or Triggered /Toggle
• D type Flip-flop or Data / Delay
• JK type Flip-flop

After you have looked at the information about flip-flops, you can use some LabView simulations to get more familiar with how the flip-flops function. To start the simulations now, you should move onto the next webpage, Flip-Flop Simulations.

SR Flip-flop - (Set / Reset)

This type of flip-flop has two inputs: Set and Reset. Two outputs: Q and Q' (Q' being the inverse of Q). The SR flip-flop can also have a clock input for a level driven circuit as opposed to a pulse driven circuit.

The operation of an SR flip-flop is as follows: The Set input will make Q goto 1 i.e. will 'set' the output. The Reset input will make the output Q goto 0 i.e. reset the output.
The scenerio of having both Set and Reset at logic 1 is not allowed as this is not a logical pair of inputs.

Knowing the above, we can layout the operating characteristics and the state change table:

There are a few different ways SR flip-flops can be made. They can be pulse driven or clock (and therefore level are used) driven. For the state change diagram above either a pulse or level input can be implied. When using the state change table to describe pulses, a '1' implies a pulse should be applied, where '0' implies that no pulse should exist at this state.
For either a pulse driven circuit or a clock driven circuit, the following applies: An 'X' means a pulse / level may or may not be applied. The reason behind this is because no matter of the input (0 or 1), the output will always goto the same value. It is because of this fact that this is considered a 'don't care' input. Hence 's' and 'r' are 'don't care' sets of 'S' and 'R' respectivly ('s' leads to the same output as 'S' and that is why 's' is a subset of 'S').

T flip-flop (Triggered / Toggle)

The T type flip-flop is a single input device: T (trigger). Two outputs: Q and Q' (where Q' is the inverse of Q).

The operation of the T type flip-flop is as follows: A '0' input to 'T' will make the next state the same as the present state (i.e. T = 0 present state = 0 therefore next state = 0). However a '1' input to 'T' will change the next state to the inverse of the present state (i.e. T = 1 present state = 0 therefore next state = 1).

Knowing the above, we can now formalise the operating characteristics and the state change table:

The T type flip-flop is an edge driven device. Therefore you should not associate 1 and 0 with levels, but instead 1 should be considered as a pulse, and 0 as no pulse.

Notice that if a clock signal was tied to T, the output Q would be a clock signal at approximatly half the frequency of T. This property makes the T flip-flop a good candidate for applications such as frequency division.

D type flip-flop (Delay)

The D type flip-flop has one data input 'D' and a clock input. The circuit edge triggers on.the clock input. The flip-flop also has two outputs Q and Q' (where Q' is the reverse of Q).

The operation of the D type flip-flop is as follows: Any input appearing (present state) at the input D, will be produced at the output Q in time T+1 (next state). e.g. if in the present state we have D = 0 and Q = 1, the next state will be D = anything and Q = 0.

Knowing the above, we can now generate the state change table and the operating characteristics.

The operation of the D type delays any input by exactly one clock cycle (given an instantanious response time i.e. a perfect flip-flop). Cascading several D type flip-flops together can produce delaying circuits, possible applications could be for matching time delays in digital television systems.

JK flip-flop

The JK type flip-flop consists of two data inputs: J and K, and one clock input. There are again two outputs Q and Q' (where Q' is the reverse of Q).

The JK flip-flop operations are quite complicated to understand by text alone. So here we will simply see the operating characteristics diagram and then discuss it.

1. When J=K=0, the current output will carry through to the next state. e.g. Current state Q = Next state Q
2. When J=0 and K=1, the next state output will be put to 0. This happens regardless of the present state output.
3. When J=1 and K=0, the next state output will be asserted (put to 1). This happens regardless of the present state output.
4. When J=K=1, the next state output will be the inverse of the current state output. e.g. Current state Q' = Next state Q.

Knowing the above we can now construct the state change table:

Lets discuss this state change table with respect to the operating characteristics diagram. There actually exists two operating characteristics that satisfy every possible output combination. This means there should be some 'don't care' terms with each output combination (as our diagram shows). In the list below we shall see how each of the terms

1. Two conditions exist so that the next state is 0 while the present state is also 0. From the operating characteristics diagram, we can see that condition A and B would both satisfy this scenerio. The common term to make this scenerio true is J=0. We dont care about K, as K=1 or K=0 while J=0 will work. Hence the 'don't care' term is K,
2. Operating characteristics C and D both satisfy this scenerio. The common term is again J, as the situation is solved by J=1 and either K=0 or K=1, therefore the 'don't care' term is K as shown on the state change table.
3. When the output goes from 1 to 0, there are two characteristics that will allow this to happen; B and D. K=1 and J can be equal to 1 or 0. Therefore in this case, J is the 'don't care' term.
4. When the JK flip-flop remains at logic, it means that either A or C of the four operating characteristics have been applied. K must equal 0 in either case, but J could have been equal to 1 (A) or 0 (C). Because of this, J is the 'don't care' term.

The JK flip-flop can actually be reconfigured so that it can perform the operation of some of the other flip-flops that are discussed above. For example, if the two inputs J and K are tied together, then the output characteristics are fixed to A and D. This precisely matches the characteristics of a T type flip flop. Also to note, because the way a JK is made, you may replace an SR flip-flop with a JK flip-flop without a change in operation. However you cannot replace a JK flip-flop with an SR flip-flop as a S=1 R=1 condition is not allowed, but a J=1 K=1 condition is permitted.

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