Chapter 2. - Hazards

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In this section we will be looking at hazards, what causes hazards to occur and critcally what you as a future designer can do to prevent hazards occuring in the first place.

What are Hazards ?

Hazards in any system are obviously an un-desirable effect caused by either a deficency in the system or external.influences. In digital logic hazards are usually refered to in one of three ways:

These logic hazards are all subsets of the same problem: - When changes in the input variables do not change the output due to some form of delay caused by logic elements (NOT, AND, OR gates etc), this results in the logic not performing its function properly.

This is however a temporary problem, and the logic will finally come to the desired function. Despite the logic arriving at the correct output, it is imeritive that hazards be eliminated as they can have an effect on other systems. Imagine hazards like this in a piece of hospital equipment.

Static Hazards

Definition:- "When one input variable changes, the output changes momentarily when it shouldn't"

This particular type of hazard is usually due to a NOT gate within the logic. We can see the effects of the delay in the circuit from the following flash animation.


The hazard can be dealt with in two ways:

  1. Insert another (additional) delay to the circuit. This then eliminates the static hazard.

  2. Eliminate the hazard by inserting more logic to counteract the effects (Note this makes assumptions that the logic will fail)

The first case is the most used of the two options. This is because it does not make assumptions about the logic, instead the method adds redundancy to overcome the hazard.

To solve the hazard we shall use our previous example and apply a theory that 'Huffman' discovered.
The insertion of a redundant loop can elimate a static hazard.

In the next example, it will also be evident that there will not be a situation where a static '0' occurs. A static '0' hazard is one which briefly goes to '1' when it should remain at '0'. A static '1' hazard is the reverse of this situation, i.e. the output should remain at '1' yet under some condition it briefly changes state to '0' (something we shall see in the following example)..

Example of Static Hazards
The Static '1' Hazard.

Let us consider an imperfect circuit that suffers from a delay in the physical logic elements i.e. AND gates etc.
The simple circuit performs the function:

f = X1.X2 + X1'.X3

and the logic diagram can be shown as follows:

<insert flash logic animation>

If we first look at the starting diagram, it is clear that if no delays were to occur, then the circuit would function normally. However since this isnt a perfect circuit, and an error occurs when the input changes from 111 to 011. i.e. When X1 changes state.
Now we know roughly how the hazard is occuring, for a clearer picture and the solution on how to solve this problem, we look to the Karnaugh Map:

This Karnaugh Map shows the circuit. The two gates are shown by solid rings, and the hazard can be seen under the dashed ring. The theory proved by Huffman tells us that by adding a redundant loop 'X2X3' this will elimate the hazard. So the resulting logic is of the form shown in the next figure.

So our original function is now: f =X1.X2 + X1'.X3 + X2.X3

Now we can see that even with imperfect logic elements, our example will not show signs of hazards when X1 changes state. This theory can be applied to any logic system. Computer programs deal with most of this work now, but for simple examples it is quicker to do the debugging by hand. When there are many input variables (say 6 or more) it will become quite difficult to 'see' the errors on a Karnaugh map.


Worked question.
Consider the following circuit and identify the hazard. Use the same method as the example above to remove the hazard. For a complete solution, goto this page. If you have completed this, or you feel confident with this topic, then move on to dynamic hazards.

Dynamic Hazards

Definition:- "A dynamic hazard is the possibility of an output changing more than once as a result of a single input change"

Dynamic hazards often occur in larger logic circuits where there are different routes to the output (from the input). If each route has a different delay, then it quickly becomes clear that there is the potential for changing output values that differ from the required / expected output.
e.g. A logic circuit is meant to change output state from '1' to '0', but instead changes from '1' to '0' then '1' and finally rests at the correct value '0'. This is a dynamic hazard.

As we shall see, dynamic hazards take a more complex method to resolve (which we shall not cover). Let us explain this more with a slide show. The example shows how a dynamic hazard can occur but now how to solve it.

As a final note on dynamic hazards, it should be noted that if all static hazards have been eliminated from a circuit, then dynamic hazards cannot occur.

Function Hazards

Function hazards are non-solvable hazards which occurs when more than one input variable changes at the same time. Hazards such as function hazards can not be logically eliminated as the problem lies with actual specification of the circuit. The only real way to avoid such problems is to restrict the changeing of input variables so that only one input should change at any given time.

Restrictions are not always possible, for instance let us imagine some logic circuit that has two inputs. One input is used for a clock signal, and the other is connected to a random noise source that we wish to measure. It should be clear that restrictions in this case would not be an effective solution.

The simplest example of this is the exclusive-or function.

In this scenerio it is quite difficult to see how a hazard could occur if the circuit is built up on the same couple of chips. However let us imagine that some circuit designer has split this function across different chips (i.e. one NOT gate on one chip and the other NOT gate is implemented on another chip across the PCB somewhere)

Let us setup the initial state of our circuit. A = 1, B = 0. Now lets say there is a delay in the NOT gate marked (X). The inputs now change simultaneuoulsy so that A = 0 and B = 1 (remember in a equally delayed circuit or a perfect circuit, the circuit output would match the specification).
If we observe what the circuit should do, and do not change the output of the NOT gate X (this simulates a delay in gate X), it should be clear that the output of the circuit changes. Now we change the output of NOT gate X and the circuit goes back to the proper state.

The most effective way to solve this hazard would be to carefully design the PCB so that delays are all equal, or at least match the delays on each path. i.e. Delay of A's path = Delay of B's path. Yet adding more gates to the circuit by the same methods as descibed in dynamic and static hazards will not work as Huffmans method cannot be applied.

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