From the previous section, we can see that minterms of an input are
generated from decoders. This is of limited use on its own, so decoders
are used with additional logic at the output stage. Let us say we have
a 2 to 4 line (non inverted) decoder and need a function of the following
Z = Sum(2,3) = A./B + A.B
We can use the minterms from the decoder with one single OR gate to
make up the above function. This is simple. However there is nothing
stopping us derive more than one function. So Z1 = Sum(1,0) Z2 = Sum(1,3)
and Z3 = Sum(2,3). We can use 3 OR gates and we now have 3 different
The resulting logic is shown as follows:
When we are trying to implement functions like this using inverted
decoders, we can use NAND gates instead of OR gates. This can be proved
by use of De Morgan's theorems:
The logic we currently have looks like this; (X+Y) = Z
Our input stage is then inverted because of the decoder, so if we still
use OR gates our Z will be wrong; (X'+Y') != Z
However we can correct this by adding two NOT gates, however this is
quite wasteful; (X''+Y'') = Z
Now using De Morgan we can re-write as; (X'.Y')' = Z as X'+Y' = (X.Y)'
This the exact circuit that we have, inverted inputs from the decoder
and now the usage of NAND gates.
Minimization of output logic
The minimization process for multiple outputs from any device is simple.
This is best shown using an example.
Using a 3-8 decoder (non inverted), implement the following output functions.
Z0 = ∑ (2,3,5,6)
Z1 = ∑ (0,1,2,3)
Z2 = ∑ (0,1,5,6)
Z3 = ∑ (0,1,7)
To simplify the terms, we can rewrite them in this form to identify
Z0 = _ _ 2 3 _ 5 6 _
Z1 = 0 1 2 3 _ _ _ _
Z2 = 0 1 _ _ _ 5 6 _
Z3 = 0 1 _ _ _ _ _ 7
Note: We can pair (0,1), (2,3) and (5,6) as these are common across
several needed outputs.
The solution shown below uses 7 x two input OR gates and 1 x 3-8 decoder
to create the needed functions.