Synchronous and Asynchronous Circuits

 Classification Of Sequential Circuits

Sequential circuits fall into two classes: synchronous and asynchronous.

 In synchronous circuits the input are pulses (or levels and pulses) with certain restrictions on pulse width and circuit propagation delay. Therefore synchronous circuits can be divided into clocked sequential circuits and uncklocked or pulsed sequential circuits.

In a clocked sequential circuit which has flip-flops or, in some instances, gated latches, for its memory elements there is a (synchronizing) periodic clock connected to the clock inputs of all the memory elements of the circuit, to synchronize all internal changes of state.

Hence the operation of the entire circuit is controlled and synchronized by the periodic pulses of the clock.


On the other hand in an unclocked or pulsed sequential circuit, such a clock is not present. Pulse mode circuits require two consecutive transitions between 0 and 1 - that is a 0-pulseor a 1 pulse to alter the circuit’s state. A pulse -mode circuit is designed to respond to pulses of certain duration; the constant signals between the pulses are “null” or “spacer” signals, which do not affect the circuit’s behavior

From the above block diagrams we can note the following:

1)     Pulse outputs: For pulsed sequential circuits these occur only for the duration of the respective input pulse and in some cases for duration considerably less. For clocked sequential circuits these outputs occur for the duration of the clock pulse.


2)     Level outputs: These change state at the start of the respective input or clock pulse and remain in that state until the next state of output is required.

A requirement of synchronous sequential circuits is that the duration of the activating pulse or clock pulse should be sufficiently low in value that the pulse (or clock) has disappeared by the time the secondaries (the flip-flops outputs) have taken on their new value; otherwise the circuit will change state again. This means that the storage elements (flip-flops) should be edge-triggered devices (for example: D-type flip-flop, the JK flip-flop and their derivatives).


The circuit is considered to be asynchronous if it does not employ a periodic clock signal C to synchronize its internal changes of state. Therefore the state changes occur in direct response to signal changes on primary (data) input lines, and different memory elements can change state at different times.

In asynchronous sequential circuits the inputs are levels and there are no clock pulses; the inputs events drive the circuit.

In general, an asynchronous circuit does not need the precise timing control supported by flip-flops. It may therefore contain latches rather than flip-flops. In many cases, an asynchronous circuit simply relies on the propagation delays of its component gates and connections, combined with the circuit’s feedback structure, to implement its memory functions.


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